Welcome to Efficient Computing Hardware and System Lab at SJTU!
We are a group of people working at the intersection areas of computer architecture, digital circuit design, and low-level software, for efficient, fast, and reliable computing.
Recent News
[Feb 2026] One of our work is accepted to TCAD 2026. It proposes a runtime scheduling mechanism for hard and soft real-time tasks on heterogenous GPU architectures.
[Dec 2025] Our collaboration work on real-time and timing critical LLM (TimeBill: Time-Budgeted Inference for Large Language Models) is selected as HuggingFace Daily Papers (https://huggingface.co/papers/2512.21859).
[Nov 2025] One of our collaboration paper is accepted to AAAI 2026. It proposes a Real-Time LLM for time-critical applications. Congratulations to Qi Fan and collaborators.
[Nov 2025] One paper is accepted to DATE 2026. It proposes a RL-based combinational compression for neural networks. Congratulations to Yingtao and collaborators.
[Nov 2025] One survey paper is accepted to TODAES 2026. It surveys hardware tampering detection via power delivery network and signal trace. Congratulations to Minqing and collaborators.
[Oct 2025] One paper is accepted to TCAD 2025. The work is about lightweight neural network with early exits. Congratulations to Yingtao and collaborators.
[Oct 2025] We received industry fundings (250K RMB) to explore and design the FPGA-based Tensor Accelerator.
[Oct 2025] Yinchen, Jiace, Xingzhe won the Embedded Systems Software Competition Winner at ACM/IEEE Embedded Systems Week. Congratulations to them.