About Me
I am currently an Associate Professor at UM-SJTU Joint Institute (JI) at Shanghai Jiao Tong University, where I am leading the Intelligent Circuits, Architectures, and Systems (iCAS) Lab at SJTU. I received my Ph.D. in Computer Engineering from the University of Virginia, where I was part of the High-performance Low-power (hplp) Lab led by Prof. Mircea Stan. I also hold a M.S. degree in Electrical and Computer Engineering from the University of Florida and a B.Eng degree from Xidian University.
Before joining JI, I was a Senior SoC Design Engineer at NVIDIA (US), where I contributed to the first few generations of industry-leading BlueField® Data Processing Unit (DPU). I also worked at IBM Thomas J. Watson Research Center as an adjunct researcher. A blend of academia and industry experiences shaped my current focus of research, which is on intelligent chip system design, electronic design automation (EDA), microarchitectures and accelerators. My previous research projects have resulted in seven chip tapeouts (including 14nm and 7nm), over 70 peer-reviewed research articles, two books, one book chapter and multiple US/China patents.
I was also a co-author of several best paper awards (IEEE SOCC 2022, LASCAS 2019, SELSE 2017), a receipt of the IEEE CASS Pre-doctoral Fellowship and several other research awards. I serve as the Associate Editor-in-Chief (AEiC) for the IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and Associate Editor for Elsevier Integration, the VLSI Journal, and have served as PC member or chair positions for over 30 international conferences, such as DAC, CICC, ICCAD, FCCM, AICAS, ISICAS, ISCAS, etc. I am a IEEE CASS Distinguished Lecturer (2026-2027), an IEEE/ACM/CCF Senior Member, and the co-founder and co-chair for the IEEE SSCS Webinars for Young Excellence (WYE) program. I frequently teach computer engineering courses ECE4700J Computer Architecture (Undergrads Capstone), ECE4810J SoC Design (Grads/Undergrads Cross-listed) and ECE6707J Modern Digital VLSI Design (Grads Gateway).
Research Interests
Recent News
To Post-doc Candidates
I have 1-2 openings for Post-doc researchers who are interested in one or more of the following research areas:
- Electronic Design Automation
- Low-power Circuit and Architectures
- HW/SW co-design for Edge AI
- Circuit Reliability
- Advanced Packaging (Chiplet, 3DIC)
Interested candidates can send your updated CV together with 3 representative publications to Dr. Xinfei Guo via xinfei.guo@sjtu.edu.cn with the following subject line: [Post-Doc Application] + First Name+Last Name.
To Prospective Graduate Students
I am actively looking for self-motivated graduate students (Masters & Ph.D.) to work with me to tackle the most challenging yet practical research problems in the field of digital VLSI design, Electronic Design Automation (EDA) or Computer Architecture. Please don’t hesitate to send me an email with your latest CV/transcript.
To Undergraduate Students
I am always looking for self-motivated undergraduate researchers (who can start asap) to work on projects in the field of low power chip design, machine learning assisted chip design automation and hardware acceleration techniques. You can join through the SJTU Summer Internship program or take credits (through ECE4900) or participate through other university level research programs (such as IPP, PRP or CTP). You will have opportunities to publish at top conferences and journals (as the first author), and will also gain practical skills in digital design, large-scale SoC design with advanced technology node, machine learning or the whole chip design process in an industry-like research environment. Please feel free to stop by or send me an email with your latest CV/transcript.