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Book/Book Chapters

  • B3 X. Guo, R. Wang, F. Hu, X. Wu, “AI-Powered Vehicles: Computing Power and Chips for Intelligent Driving”, ISBN 9787111799894, China Mechanical Industry Press, 2026. (In Chinese)
  • B2 X. Guo*, L. Zhu, Y. Cai, “Harnessing Graph Learning for Efficient Timing Signoff”, in AI-Enabled Electronic Circuit and System Design: From Ideation to Utilization, ISBN 9783031714351, Springer Nature, 2025. (link)
  • B1 X. Guo*, M. R. Stan, “Circadian Rhythms for Future Resilient Electronic Systems – Accelerated Active Self- Healing for Integrated Circuits,” Springer, 2020. (link) (Amazon)

Journals

  • J21 Z. Yu, H. Zhao, Z. Li, Y. Pan∗, X. Guo*, “Stall-Free Software–Hardware Co-Design for Perception-Driven Contrast-Limited Adaptive Histogram Equalization”, Accepted by ACM Transactions on Embedded Computing Systems (TECS), To appear. (link)
  • J20 Y. Hu, Y. Pan, X. He, X. Guo, H. Wang, K. Wang, Y. Cao, Z. Xu, “TCaN: Temporal Calibration Network for Dynamic Multimodal Sentiment Analysis with Adaptive Modality Fusion”, Accepted by IEEE Transactions on Affective Computing (TAC), Early Access, 2026. (link)
  • J19 J. Shaik, F. Hu, L. Zhu, S. Singha, X. Guo*, “Extending Silicon Lifetime: A Review of Design Techniques for Reliable Integrated Circuits”, Accepted by ACM Computing Surveys (CSUR), vol. 58, no. 14, pp. 1-35, July 2026. (link)
  • J18 X. Wu⋄, Z. Li⋄, F. Hu⋄, T. Lin, X. Zhao, R. Wang, X. Guo*, “Shift Left Techniques in Electronic Design Automation: A Survey”, Accepted by ACM Computing Surveys (CSUR), vol. 58, no. 13, pp. 1-35, 2026. (link) (⋄: Equal Contribution)
  • J17 X. Zhao⋄, Y. Wang⋄, Z. Li, Y. Li, Y. Pan, X. Guo*, “An EDA Physical Design Rectilinear Floorplan Benchmark Dataset (R-Zoo)”, Accepted by IEEE Data Descriptions (IEEE-DATA), vol. 3, pp. 256-264, 2026. (link) (⋄: Equal Contributions)
  • J16 X. Zhao, Z. Li, Y. Cai, J. Chen, Y. Pan, X. Guo*, “DARE: Enriching Physical Dataflow Awareness for Macro Placement Optimization”, Accepted by ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 31, no. 5, Art. 93, 2026. (link)
  • J15 Y. Su, Y. Wang*, Y. Pan, N. Xiang, H. Zhang, Y. Chen, Z. Xu, J. Smith, X. Guo*, “Algorithm-Hardware Co-Design of Binary Neural Network for Efficient Super Resolution on FPGA”, Accepted by Integration, the VLSI Journal, vol. 108, Art. 102674, 2026. (link)
  • J14 K. Cheah, F. Q. Chua, Y. Zhang, Y. Ji, Y. Zhang, X. Guo, H. Ramiah, and Y. Li, “A Corpus Of Synthesizable Verilog RTL Modules Dataset for EDA Research (CORE)”, Accepted by IEEE Data Descriptions (IEEE-DATA), vol. 2, pp. 416-424, 2025. (link)
  • J13 Y. Ouyang, Y. Liang, Q. Li, X. Guo, Y. Luo, D. Wu, H. Wang, Y. Pan, “Back to fundamentals: Low-level visual features guided progressive token pruning”, Accepted by Journal of Systems Architecture (JSA), Volume 168, November 2025. (link)
  • J12 R. Wang, Z. Wang, T. Lin, J. Raby, M. Stan, X. Guo*, “Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs”, Accepted by IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 15, no. 4, pp. 659-673, 2025. (link)
  • J11 X. He, Y. Pan, Z. Xu, Z. Li, X. Guo, C. Yang, “AL-HCL: Active Learning and Hierarchical Contrastive Learning for Multimodal Sentiment Analysis with Fusion Guidance”, Accepted by IEEE Transactions on Affective Computing (TAC), vol. 17, no. 1, pp. 303-316, 2026. (link)
  • J10 X. He, Y. Pan, X. Guo, Z. Xu, C. Yang, “Scale-Selectable Global Information and Discrepancy Learning Network for Multimodal Sentiment Analysis and Depression Detection”, Accepted by IEEE Transactions on Affective Computing (TAC), vol. 16, no. 4, pp. 3169-3182, Oct. 2025. (link)
  • J9 X. Zhao, R. Xu, Y. Gao, V. Verma, M. Stan, X. Guo*, “Edge-MPQ: Layer-Wise Mixed-Precision Quantization with Tightly Integrated Versatile Inference Units for Edge Computing”, IEEE Transactions on Computers (TC), vol. 73, no. 11, pp. 2504-2519, Nov. 2024. (link)
  • J8 J. Shaik, X. Guo*, S. Singhal, “Impact of Aging and Process Variability on SRAM-based In-Memory Computing Architectures”, IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 6, pp. 2696-2708, June 2024. (link)
  • J7 X. Guo*, “Active Accelerated Recovery for Combating Chip Aging Issues – Opportunities and Challenges”, Journal of Electronics & Information Technology, vol. 45, no. 11, pp. 1-12, 2023. (Invited paper) (In Chinese) (Featured Article)
  • J6 M. El-Hadedy⋄*, X. Guo⋄*, K. Yoshii, Y. Cai, R. Herndona, B. Bantaa, W. Hwu, “RECO-ASCON: Reconfigurable ASCON Hash Functions for IoT Applications”, Integration, the VLSI Journal, vol. 93, pp. 102061, 2023. (⋄ Equal contributions)
  • J5 X. Guo*, M. El-Hadedy, S. Mosanu, X. Wei, K. Skadron, M. Stan, “Agile-AES: Implementation of Configurable AES Primitive with Agile Design Approach”, Accepted by Integration, the VLSI Journal, 2022. (link)
  • J4 P. Guerrero, T. Tracy II, X. Guo, M. Lenjani, K. Skadron and M. Stan, “Towards on-node machine learning for ultra-low-power sensors using asynchronous Sigma Delta streams,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 16, No. 4, Article 44 , doi.org/10.1145/3404975, 2020. (link)
  • J3 X. Guo, V. Verma, P. Guerrero, S. Mosanu, M. Stan, “Back to the Future: Digital Circuit Design in the FinFET Era,” Journal of Low Power Electronics (JOLPE), Vol. 13, No. 3, pp. 338–355, DOI 10.1166/jolpe.2017.1489, September 2017. (Invited Paper) (link) (Invited Talk video)
  • J2 X. Guo, M. Stan, “Implications of Accelerated Self-Healing as a Key Design Knob for Cross-Layer Resilience”, INTEGRATION, the VLSI journal, DOI 10.1016/j.vlsi.2016.10.008, vol. 56, pp. 167-180, 2017. (pdf)
  • J1 M. El-Hadedy, X. Guo, M. Margala, M. Stan, K. Skadron, “Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.” Journal of Signal Processing Systems (JSPS), DOI 10.1007/s11265-016-1199-1, (2016): 1-18. (pdf)

Conferences

  • C59 J. Shaik, S. Picardo, F. Hu, X. Wu, S. Singha, and X. Guo∗, “Aging Analysis of CMOS Synaptic Circuits with Simplified Leaky Integrate-and-Fire Neurons”, Accepted by IEEE Multicore and Many-core Systems-on-Chip Forum (MCSOC), Shanghai, China, December 2026.
  • C58 T. Lin, R. Wang, J. Shaik, X. Guo∗, “PIMScope: Augmenting Ramulator 2.0 with Command-Level LPDDR-PIM for Transformer Inference”, Accepted by IEEE Multicore and Many-core Systems-on-Chip Forum (MCSOC), Shanghai, China, December 2026.
  • C57 F. Hu, X. Wu, H. Wang, J. Shaik, S. Singha, and X. Guo*, “RESIST: Residual Reinforcement Learning for Lifespan Clock Tree Reliability Optimization”, Accepted by IEEE International Conference on Computer Design (ICCD), Hong Kong, China, November 2026.
  • C56 R. Xu, Y. Ren, W. Qian, X. Guo*, “Tri-Balancing Act: Noise-Guided Mixed-Precision Search for Accuracy–Energy–Resilience Co-Optimization”, Accepted by International Conference on Computer-Aided Design (ICCAD), San Jose, CA, US, November 2026.
  • C55 Y. Gao, L. Dai, J. Yin, X. Guo, M. Stan, “FlexPosit: Tunable Fractional Precision for LLM Inference Accelerators”, Accepted by IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece, November 2026.
  • C54 Y. Liu, Z. Chen, Y. Gu, C. Wu, X. Guo, D. Xue, J. Li, M. Guo, P. Liu, J. Lv, “HUME: Heterogeneous Unified Mirroring with Encoded Replica for Resilient Tiered Memory Systems”, Accepted by IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece, November 2026.
  • C53 Z. Ning, X. Liu, R. Xu, X. Guo, Z. He, X. Qiu, “NimbleMoE: Collaboration-Aware Expert Merging with Sparse Compensation for Efficient Mixture-of-Experts LLMs”, Accepted by The 2026 Conference on Empirical Methods in Natural Language Processing (Main) (EMNLP), Budapest, Hungary, October 2026.
  • C52 R. Xu, Y. Su, J. Raby, Y. Wang, Y. Pan, X. Guo*, “DDPA: Dynamic-Dimensional Piecewise Approximation for Unified Activation Function Acceleration”, Accepted by IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Fukuoka, Japan, October 2026.
  • C51 L. Zhu, X. Wu⋄, F. Hu⋄, L. Li, Q. He, Y. He and X. Guo∗, “PRISM: Beam-Search Technology Mapping via Learned Physical Timing”, Accepted by IEEE International SoC Conference (ISOCC), Incheon, South Korea, October 2026. (⋄: Equal Contributions)
  • C50 J. Raby, Y. Su, R. Xu, Y. Wang, Y. Pan and X. Guo*, “Characterizing CPU-FPGA Boundary Cost Across Transformer Partitioning Strategies on Edge SoCs”, Accepted by International Conference on Intelligent Technology and Embedded Systems (ICITES), Hangzhou, China, September 2026.
  • C49 L. Jiang, S. Ding, R. Xu, X. Guo, X. Lu, “Energy Efficient Analog Neural Network via SHAPE: Sensitivity-Aware Heterogeneous Power Allocation Framework”, Accepted by IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Ha Long Bay, Vietnam, September 2026.
  • C48 F. Hu, J. Shaik, X. Guo*, “Beyond Iterative Search: Intelligent Generative GATv2 Framework for Analog Sizing”, Accepted by IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Ha Long Bay, Vietnam, September 2026.
  • C47 Y. Cai, X. Zhao, H. Wang, J. Shaik, M. El-Hadedy, X. Guo*, “AutoTimer: An LLM-Powered Assistant for Timing Report Analysis and Physical Design Closure”, Accepted by IEEE International Conference on LLM-Aided Design (ICLAD), Stanford, CA, July 2026.
  • C46 Z. Li⋄, K. Tian⋄, F. Hu, Z. Li, X. Wu, H. Zhang, S. Chen, J. Zhai*, X. Guo*, K. Zhao, “ChiPlanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems”, Accepted by ACM/IEEE Design Automation Conference (DAC), Long Beach, USA, July 2026. (⋄ Equal contributions)
  • C45 L. Zhu, T. Tseng, Y. Pan, Q. He, X. Guo*, “CircuitS2L: Circuit Dataset Augmentation via Generative Featuring and Supervised Labeling”, Accepted by IEEE International Symposium on Circuits & Systems (ISCAS), Shanghai, China, May 2026.
  • C44 Z. Ning, J. Shao, R. Xu, X. Guo, J. Zhang, C. Zhang, X. Li, “CAS-Spec: Cascade Adaptive Self-Speculative Decoding for On-the-Fly Lossless Inference Acceleration of LLMs”, Accepted by The Thirty-ninth Annual Conference on Neural Information Processing Systems (NeurIPS), San Diego, United States, December 2025.
  • C43 C. Che, Y. Jiang,X. Guo*, K. Lei*, R. Martins, P. Mak, “A Linear-Regression-Assisted Trimming Scheme for CMOS Voltage Reference”, Accepted by IEEE International Symposium on Circuits & Systems (ISCAS), London, United Kingdom, May 2025.
  • C42 X. Zhao, J. Chen, Z. Li, Y. Cai, X. Guo*, “IncreDFlip: Incremental Dataflow-Driven Macro Flipping for Efficient Macro Placement Refinement”, Accepted by International Symposium of EDA (ISEDA), Hong Kong, China, May 2025.
  • C41 X. Wu, X. Guo*, “Sketch-to-Style: Augmenting AI4EDA Dataset with Automatic Image Generative Framework”, Accepted by International Symposium of EDA (ISEDA), Hong Kong, China, May 2025.
  • C40 Y. Cai, L. Zhu, X. Guo*, “Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness”, Accepted by Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 2025.
  • C39 L. Zhu, X. Ma, S. Hao, Y. Pan, X. Guo*, “Elastic EDA: Auto-scaling Cloud Resources for EDA Tasks via Learning-based Approaches”, Accepted by IEEE International Conference on Computer Design (ICCD), Milan, Italy, November 2024.
  • C38 Y. Ouyang, W. Yang, H. Wang, Y. Pan*, X. Guo*, “MEGA: A Multimodal EEG-Based Visual Fatigue Assessment System”, Accepted by IEEE Biomedical Circuits and Systems (BIOCAS), Xi’an, China, October 2024.
  • C37 L. Zhu, Y. Cai, X. Guo*, “One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing Signoff”, Accepted by ACM/IEEE International Conference on Computer-Aided Design (ICCAD), New Jersey, USA, October 2024.
  • C36 C. Morgul,X. Guo*, M. Stan*, “Unveiling Proactive Recovery’s Preventative Impact on NAND Flash Wearout”, Accepted by IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, July 2024.
  • C35 R. Xu, Q. Duan, Q. Chen, X. Guo*, “ILD-MPQ: Learning-Free Mixed-Precision Quantization with Inter-Layer Dependency Awareness”, Accepted by IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Abu Dhabi, UAE, April 2024.
  • C34 R. Wang, R. Xu, X. Zhao, K. Jiang, X. Guo*, “CINEMA: A Configurable Binary Segmentation Based Arithmetic Module for Mixed-Precision In-Memory Acceleration”, Accepted by IEEE International Symposium on Circuits & Systems (ISCAS), Singapore, May 2024.
  • C33 X. Zhao, T. Wang, R. Jiao, X. Guo*, “Standard Cells Do Matter: Uncovering Hidden Connections for High-Quality Macro Placement”, Accepted by Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, March 2024.
  • C32 L. Zhu, X. Guo*, “Delay-Driven Physically-Aware Logic Synthesis with Informed Search”, Accepted by 41st IEEE International Conference on Computer Design (ICCD), Washington DC, USA, November 2023.
  • C31 R. Wang, J. Han, M. Stan, X. Guo*, “Hot-LEGO: Architect Microfluidic Cooling Equipped 3DICs with Pre-RTL Thermal Simulation”, Accepted by 15th IEEE International Green and Sustainable Computing Conference (IGSC), co-located with MICRO 2023, Toronto, ON, Canada, October 2023.
  • C30 Y. Gu, X. Wang, Z. Chen, C. Wu*, X. Guo*, J. Li, M. Guo, S. Wu, R. Yuan, T. Zhang, Y. Zhang, H. Cai, “Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction”, Accepted by IEEE International Test Conference (ITC), Anaheim, California, USA, October 2023.
  • C29 Y. Gao, S. Mosanu, M. Sakib, V. Verma, X. Guo, M. Stan, “LiteAIR5: A System-Level Framework for the Design and Modeling of AI-Extended RISC-V Cores”, 36th IEEE International System-on-Chip Conference (SOCC), Santa Clara, CA, USA, September 2023.
  • C28 R. Wang, X. Guo*, “A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing”, Accepted by International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, June 2023.
  • C27 L. Zhu, Y. Gu, X. Guo*, “RC-GNN: A Graph Neural Network Model for Fast and Accurate Signoff Wire Delay Estimation”, Accepted by International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, June 2023.
  • C26 X. Zhao, Y. Gao, V. Verma, R. Xu, M. Stan, X. Guo*, “Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Knoxville, TN, USA, June 2023.
  • C25 Y. Wei, S. Gong, H. Mei, L. Shi, X. Guo*, “Convolutional Neural Networks on the Edge: A Comparison Between FPGA and GPU”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, June 2023.
  • C24 X. Zhao, R. Xu, X. Guo*, “Post-training Quantization or Quantization-aware Training? That is the Question”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, June 2023.
  • C23 X. Wei, M. El-Hadedy, S. Masanu, Z. Zhu, W. Hwu, X. Guo*, “RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT”, Accepted by IEEE International System-on-Chip Conference (SOCC), Belfast, Northern Ireland, September 2022. (Best Paper Award)
  • C22 M. El-Hadedy⋄, X. Guo⋄*, “ReaLSE: Reconfigurable Lightweight Security Engines for Trusted Edge Devices”, Accepted by IEEE 4th International Conference on Circuits and Systems (ICCS), Chengdu, China, September 2022. (⋄ Equal contributions) (Best Oral Presentation Award)
  • C21 M. Morgul, M. Stan, X. Guo*, “Scheduling Active and Accelerated Recovery to Combat Aging in Integrated Circuits”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Virtual, August 2022. (Invited paper)
  • C20 M. Morgul, X. Guo, M. Stan, “Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian Rhythms”, Accepted by IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pafos, Cyprus, July 2022.
  • C19 J. Han, X. Guo, K. Skadron, M. Stan, “From 2.5D to 3D Chiplet Systems: Investigation of Thermal Implications with HotSpot 7.0”, accepted by The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (IEEE ITherm), San Diego, USA, June 2022.
  • C18 X. Wei, X. Guo*, “Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs”, International Symposium on Quality Electronic Design (ISQED), Virtual, April 2022.
  • C17 X. Guo*, “Design-for-Recovery Techniques for Combating Chip Aging Issues”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, June 2022.
  • C16 M. El-Hadedy,X. Guo, W. Hsu, K. Skadron, “Edge Crypt-Pi: Securing Internet of Things with Light and Fast Crypto-Processor,” Proc. of the Future Technologies Conference (FTC), Vancouver, Canada, November 2020. (pdf)
  • C15 P. Guerrero, T. Tracy, X. Guo, M. Stan, “Towards low-power machine learning using asynchronous computing with streams,” Proc. of International Green and Sustainable Computing Conference (IGSC), Alexandria, Virginia, October 2019. (pdf)
  • C14 P. Guerrero, X. Guo, M. Stan, “ASC-FFT: Area-efficient low-latency FFT design based on asynchronous stochastic computing,” Proc. of IEEE Latin American Symposium on Circuits and Systems (LASCAS), Armenia, Quindío, Colombia, February 2019. (Best Paper Award) (pdf)
  • C13 S. Mosanu, X. Guo, M. El-Hadedy, L. Anghel, M. Stan, “Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints”, Proc. of IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM), San Diego, CA, April 2019. (pdf)
  • C12 P. Guerrero, X. Guo, M. Stan, “SC-SD: Towards Low Power Stochastic Computing on Sigma Delta Streams,” IEEE International Conference on Rebooting Computing (ICRC), Tysons, VA, November 2018. (Video)(pdf)
  • C11 A. Roelke, X. Guo, M. Stan, “OldSpot: A Pre-RTL Model for Fine-grained Aging and Lifetime Optimization,” IEEE International Conference on Computer Design (ICCD), Orlando, FL, October 2018. (pdf) (Github)
  • C10 X. Guo, V. Verma, P. Guerrero and M. Stan, “When “things” get older – Exploring Circuit Aging in IoT Applications”, International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 2018. (pdf) (link)
  • C9 D. Kamakshi, X. Guo, H. Patel, M. Stan and B. Calhoun, “A Post-Silicon Hold Time Closure Technique using Data-Path Tunable-Buffers for Variation-Tolerance in Sub-threshold Designs”, International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 2018. (pdf) (link)
  • C8 S. Eldridge, V. Verma, X. Guo, A. Roelke, K. Swaminathan, N. Chandramoorthy, M. Cochet, A. Buyuktosunoglu, C. Vezyrtzis, R. Joshi, M. Ziegler, M. Stan, P. Bose, “VELOUR – Very Low Voltage Operation Under Resilience Constraints,” The Government Microcircuit Applications and Critical Technology Conference (GOMACTech), Miami, FL, March 2018.
  • C7 X. Guo, M. Stan, “Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery,” Proc. of IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Denver, CO, June 2017. (pdf) 
  • C6 M. El-Hadedy, X. Guo, M. Stan, K. Skadron, “PPE-ARX: Area- and Power-Efficient VLIW Programmable Processing Element for IoT Crypto-Systems,” Proc. of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Pasadena, CA, July 2017. (pdf)
  • C5 X. Guo, M. Stan, “Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery,” Proc. of 13th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE-13), Boston, MA, March 2017. (Best Paper Award) (pdf)
  • C4 X. Guo, M. Stan, “Work hard, sleep well – Avoid irreversible IC wearout with proactive rejuvenation,” Proc. of the ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, China, January 2016. (Acceptance Rate: 94/274 = 34.3%) (pdf) (slides)
  • C3 X. Guo, M. Stan, “MCPENS: Multiple-Critical-Path Embeddable NBTI Sensors for Dynamic Wearout Management,” Proc. of 11th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE-11), pp. 116-121, Austin, TX, April 2015. (pdf) (slides)
  • C2 X. Guo, W. Burleson, M. Stan, “Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques,” In Proc. of ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2014. (Acceptance Rate: 174/787 = 22%) (pdf) (.ppt) (poster)
  • C1 Y. Zhao, Y. Yang, K. Mazumdar, X. Guo, M.R. Stan, “A Multi-Output on-Chip Switched-Capacitor DC-DC Converter for Near- and Subthreshold Power Modes,” In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 2014. (pdf) (.ppt)